FIG. 1a shows a conventional testing apparatus 100 for testing a semiconductor device array. The testing apparatus 100 is applied to test a device array that has a plurality of rows and columns of devices IC0-IC63. The testing apparatus 100 transmits a clock signal CLK, an input command signal TS, and a selecting signal SS in a vertical direction of the device array and transmits a data signal DS in a horizontal direction of the device array.
When the device array is under test, the testing apparatus 100 transmits the input command signal TS in the vertical direction and transmits the data signal DS in the horizontal direction. However, the input command signal TS or the data signal DS will get delayed at the devices IC0-IC63 because of the propagation delay time of the transmission lines between the devices IC0-IC63.
FIG. 1b illustrates the input command signal TS and the data signal DS at the IC0 and the IC7. The input command signal TS and the data signal DS respectively includes a setting signal Tsetup and a holding signal Thold. At the IC0, the setting signal Tsetup of the input command signal TS and the setting signal Tsetup of the data signal DS have the same delay relative to the clock signal CLK, which is one quarter clock signal CLK (shown as t1=0.25 tCLK). Both the setting signal Tsetup of the input command signal TS and the setting signal Tsetup of the data signal DS have a co-existing period with the half period of the clock signal CLK. The co-existing period must be long enough to make sure that writing the data signal DS to the device array is successful. If the co-existing period is not long enough, the input command signal TS or the data signal DS may write error signal to the device array, due to the external signal interference of the device array. However, in FIG. 1a, the arrival time of the input command signal TS and the clock signal CLK at each device IC0-IC63 are the same because the input command signal TS and the clock signal CLK are transmitted in parallel in the device array.
When the clock signal CLK (or the input command signal TS) is transmitted to the IC16 through the IC0 and the IC8, compared with the clock signal CLK (or the input command signal TS) at the IC0, the clock signal CLK (or the input command signal TS) at the IC16 is delayed twice, as shown as t2 of the clock signal CLK (or the input command signal TS) of the IC7 in FIG. 1b. However, compared with the data signal DS at the IC0, the data signal DS at the IC7, IC15 or IC23 respectively has been delayed seven times through the IC0˜IC6, IC8˜IC14, or IC16˜IC22.
Now compare the IC0 with the IC7, the clock signal CLK has a co-existing period t1 relative to the setting time Tsetup of the data signal DS at the IC0. However, the co-existing period becomes t1′ at the IC7 because the data signal DS and the clock signal CLK encounter different delays respectively. If the co-existing period t1′ is too short, it is more likely to have test errors for the testing apparatus 100.
Therefore it is desirable to improve the drawback of the conventional testing apparatus for the semiconductor device array. The preferred embodiment has advantages in removing the testing error.